In forming a wiring pattern on a semiconductor wafer, a method is adopted in which coating material called resist is applied on the semiconductor wafer, an exposure mask (a reticle) of a wiring pattern is superposed on the resist, a visible light ray, ultraviolet rays or an electron beam is applied thereto from above, the resist is photo-sensed (exposed) and developed to thereby form the wiring pattern on the semiconductor wafer, and with this wiring pattern of the resist as a mask, the semiconductor wafer is etched to thereby form the wiring pattern.
In inspecting the mask and the pattern shape on the wafer, a critical dimension scanning electron microscope: (CD-SEM), which is a scanning charged-particle microscope, is widely used. The coordinates for performing SEM imaging for evaluating the pattern shape are called an evaluation point, and hereinafter called EP (Evaluation Point) for short. In order to image the EP with a small imaging shift amount and also with high image quality, some or all of adjustment points out of an addressing point (hereinafter referred to as AP), an auto focus point (hereinafter referred to as AF), an auto stigma point (hereinafter referred to as AST) or an auto brightness and contrast point (hereinafter referred to as ABCC) are set as needed, and at the respective adjustment points, addressing, auto focusing, auto stigma adjustment and auto brightness and contrast adjustment are performed, and then the EP is imaged. As to the imaging shift amount in the above addressing, matching between an SEM image at the AP registered in advance as a registered template, whose coordinates are already known, and an SEM image actually observed in the imaging sequence is performed, a shift amount in the matching is taken as a shifting amount of the imaging position, and corrected. The evaluation point (EP), and the adjustment points (AP, AF, AST, ABCC) are collectively called the imaging point. The size and coordinates and the imaging conditions of the EP, the imaging conditions and adjusting methods of the respective adjustment points and the imaging order (or the adjusting sequence) of the respective imaging points, and the above registered template are managed as an imaging recipe, and the SEM images the EP according to the imaging recipe.
The recipe has been manually generated heretofore by an SEM operator, so the labor and time are required. Further, in order to decide the respective adjustment points and register the registered template in the recipe, it is necessary to actually image the wafer at a low power, resulting in that the generation of a recipe is one of the causes of lowering the operating ratio of the SEM apparatus. Further, with the development to the microstructure and the complicatedness of a pattern, the number of points requiring evaluation remarkably increases, so that the manual generation of the recipe is becoming unrealistic from a viewpoint of labor and generation time.
Therefore, concerning the imaging recipe, for example, a semiconductor inspection system is disclosed in which the AP is determined based on design data on a circuit pattern of a semiconductor described in the GDS II form, and further data in the AP is picked from the design data and registered as the registered template in the imaging recipe (Patent Literature 1: JP-A No. 2002-328015 official gazette). In that system, it is not necessary to image an actual wafer only for the purpose of deciding the AP and registering the registered template, so that the improvement in operating ratio of the SEM can be achieved. Further, the system has such a function that when an SEM image at the AP (an actual imaging template) is obtained in the actual imaging sequence, matching between the actual imaging template and the registered template of design data is performed, and an SEM image corresponding to the position of the registered template of the design data is re-registered as the registered template in the imaging recipe, and hereinafter the registered template of the re-registered SEM image is used for the addressing processing. Further, the system has a function of automatically detecting a characteristic pattern part from the design data, and registering the same as the AP.
As the EP, cited are a designation point from a user and a critical portion where device failure is liable to occur called a hot spot output from an EDA (Electronic Design Automation) tool or the like, and feedback such as shape correction for a mask pattern and an alteration of the semiconductor manufacturing process condition is performed based on the pattern dimensional values at these EPs to thereby achieve a high yield. The wiring pattern has been advanced to microstructure and high densification to meet the recent needs of high speed and high integration of the semiconductor device, and super-resolution exposure technique represented by Optical Proximity Correction (OPC) has been introduced. With this introduction, the mask pattern becomes complicated so that simulation prediction for a pattern shape transferred on a wafer and inspection for the actually transferred pattern shape become more important.    [Patent Literature 1] JP-A No. 2002-328015 official gazette